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HT82V26A 16-bit ccd/cis analog signal processor rev. 1.00 1 august 16, 2005 features operating voltage: 5v (typ.) low power consumption at 400mw (typ.) power-down mode: under 2ma (typ.) 16-bit 30 msps a/d converter guaranteed won t miss codes 1~6 programmable gain correlated double sampling 250mv programmable offset input clamp circuitry internal voltage reference multiplexed byte-wide output (8+8 format) programmable 3-wire serial interface 3v/5v digital i/o compatibility 3-channel operation up to 30 msps 2-channel (even-odd) operation up to 30 msps 1-channel operation up to 25 msps 28-pin ssop/sop package (lead-free on request) general description the HT82V26A is a complete analog signal processor for ccd imaging applications. it features a 3-channel architecture designed to sample and condition the out- puts of tri-linear color ccd arrays. each channel con- sists of an input clamp, correlated double sampler (cds), offset dac and programmable gain amplifier (pga), and a high performance 16-bit a/d converter. the cds amplifiers may be disabled for use with sen - sors such as contact image sensors (cis) and cmos active pixel sensors, which do not require cds. the 16-bit digital output is multiplexed into an 8-bit out- put word that is accessed using two read cycles. the in- ternal registers are programmed through a 3-wire serial interface, which provides gain, offset and operating mode adjustments. the HT82V26A operates from a single 5v power supply, typically consumes 400mw of power. applications flatbed document scanners film scanners digital color copiers multifunction peripherals technical document tools information faqs application note
block diagram pin assignment HT82V26A rev. 1.00 2 august 16, 2005

! ! " # $ % % # " & ! ' & ( ) ) * + * ) ) ) ) ) " ) " ) " ( * * + , , - , ( ( + , ( + - % - . - - / - 0 - - - - - 1 % . / - 0 / . % 1 - 0 ) ) ) " ( * * + ) " ) " * + * ) ) ( , + , , - , ( ) ) . 2 3 4 / 0 - 1 2 3 4

pin description pin no. pin name i/o description 1 cdsclk1 di cds reference clock pulse input 2 cdsclk2 di cds data clock pulse input 3 adcclk di a/d sample clock input for 3-channels mode 4oe di output enable, active low 5 drvdd p digital driver power 6 drvss p digital driver ground 7~14 d7~d0 do digital data output 15 sdata di/do serial data input/output 16 sclk di clock input for serial interface 17 sload di serial interface load pulse 19, 27 avss p analog ground 18, 28 avdd p analog supply 20 refb ao reference decoupling 21 reft ao reference decoupling 22 vinb ai analog input, blue 23 cml ao internal reference output 24 ving ai analog input, green 25 offset ao clamp bias level decoupling 26 vinr ai analog input, red absolute maximum ratings supply voltage ..........................v ss 0.3v to v ss +5.5v storage temperature ........................... 50 cto125 c input voltage .............................v ss 0.3v to v dd +0.3v operating temperature .......................... 25 cto75 c note: these are stress ratings only. stresses exceeding the range specified under absolute maximum ratings may cause substantial damage to the device. functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliabil - ity. d.c. characteristics symbol parameter test conditions min. typ. max. unit v dd conditions logic inputs v ih high level input voltage (cdsclk1, cdsclk2, adcclk, oe , sck, sload) 2 v v il low level input voltage (cdsclk1, cdsclk2, adcclk, oe , sck, sload) 0.8 v v ih1 high level input voltage (sdata) 2.5 v v il1 low level input voltage (sdata) 1.5 v i ih high level input current 10 a i il low level input current 10 a c in input capacitance 10 pf HT82V26A rev. 1.00 3 august 16, 2005
symbol parameter test conditions min. typ. max. unit v dd conditions logic outputs v oh high level output voltage (sdata, d0~d7) drv dd -0.5 v v ol low level output voltage (sdata, d0~d7) 0.5 v i oh high level output current 1 ma i ol low level output current 1 ma a.c. characteristics symbol parameter test conditions min. typ. max. unit v dd conditions power supplies v add avdd 4.75 5 5.25 v v drdd drvdd 3 5 5.25 v maximum conversion rate t max3 3-channel mode with cds 30 msps t max2 2-channel mode with cds 30 msps t max1 1-channel mode with cds 25 msps accuracy (entire signal path) adc resolution 16 bits integral nonlinear (inl) 32 lsb differential nonlinear (dnl) 1 1 lsb offset error 100 100 mv gain error 5 %fsr analog inputs r fs full-scale input range 2.0 vp-p v i input limits a vss -0.3 a vdd +0.3 v c i input capacitance 10 pf i i input current 10 na amplifiers pga gain at minimum 1 v/v pga gain at maximum 5.85 v/v pga gain resolution 6 bits programmable offset at minimum 250 mv programmable offset at maximum 250 mv offset resolution 9 bits temperature range t a operating 0 70 c power consumption p tot total power consumption 400 mw HT82V26A rev. 1.00 4 august 16, 2005
timing specification symbol parameter min. typ. max. unit clock parameters t pra 3-channel pixel rate 100 ns t prb 2-channel (even-odd) pixel rate 66 ns t prc 1-channel pixel rate 40 ns t adclk adcclk pulse width 16 ns t c1 cdsclk1 pulse width 12 ns t c2 cdsclk2 pulse width 12 ns t c1c2 cdsclk1 falling to cdsclk2 rising 0 ns t adc1 adcclk rising to cdsclk1 falling 0 ns t adc2 adcclk rising to cdsclk2 falling 0 ns t ad analog sampling delay 5 ns 3-channel mode only ta c2c1 cdsclk2 falling to cdsclk1 rising 30 ns ta c2adr cdsclk2 falling to adcclk rising 30 ns 2-channel mode only tb c2adr cdsclk2 falling to adcclk rising 30 ns tb c1adr cdsclk1 rising to adcclk rising 15 ns tb c2c1 cdsclk2 falling to cdsclk1 rising 15 ns 1-channel mode only tc c2c1 cdsclk2 falling to cdsclk1 rising 15 ns tc c1adf cdsclk1 rising to adcclk falling 0 ns tc c2adr cdsclk2 falling to cdsclk1 rising 20 ns serial interface f sclk maximum sclk frequency 10 mhz t ls sload to sclk setup time 10 ns t lh sclk to sload hold time 10 ns t ds sdata to sclk rising setup time 10 ns t dh sclk rising to sdata hold time 10 ns t rdv falling to sdata valid 10 ns data output t od output delay 8 ns latency (pipeline delay) 9 cycles HT82V26A rev. 1.00 5 august 16, 2005
HT82V26A rev. 1.00 6 august 16, 2005 functional description integral nonlinear (inl) integral nonlinear error refers to the deviation of each in - dividual code from a line drawn from zero scale through a positive full scale. the point used as zero scale occurs 1 / 2 lsb before the first code transition. a positive full scale is defined as a level 1 / 2 lsb beyond the last code transition. the deviation is measured from the middle of each particular code to the true straight line. differential nonlinear (dnl) an ideal adc exhibits code transitions that are exactly 1 lsb apart. dnl is the deviation from this ideal value. thus every code must have a finite width. no missing codes guaranteed for the 16-bit resolution indicates that all the 65536 codes respectively, are present in the over-all operating range. offset error the first adc code transition should occur at a level 1 / 2 lsb above the nominal zero scale voltage. the offset error is the deviation of the actual first code transition level from the ideal level. gain error the last code transition should occur for an analog value of 1 / 2 lsb below the nominal full-scale voltage. gain error is the deviation of the actual difference be - tween the first and the last code transitions and the ideal difference between the first and the last code transi - tions. aperture delay the aperture delay is the time delay that occurs when a sampling edge is applied to the HT82V26A until the ac - tual sample of the input signal is held. both cdsclk1 and cdsclk2 sample the input signal during the transi - tion from high to low, so the aperture delay is measured from each clock s falling edge to the instant the actual internal sample is taken. internal register descriptions register name address data bits a2 a1 a0 d8 d7 d6 d5 d4 d3 d2 d1 d0 configuration 000001 3-ch cds on clamp voltage enable power down output delay 1 byte out mux 0010 rgb/ bgr red green blue delay enable cdsclk1 delay cdsclk2 delay adcclk delay redpga 010000msb lsb green pga 011000msb lsb blue pga 100000msb lsb red offset 1 0 1 msb lsb green offset 1 1 0 msb lsb blue offset 1 1 1 msb lsb internal register map configuration register the configuration register controls the HT82V26A s operating mode and bias levels. bits d6 should always be set high. bit d5 will configure the HT82V26A for the 3-channel (high) mode of operation. setting the bit d4 high will enable the cds mode of operation, and setting this bit low will enable the sha mode of operation. bit d3 sets the dc bias level of the HT82V26A s input clamp. this bit should always be set high for the 4v clamp bias, unless a ccd with a reset feed through transient exceeding 2v is used. setting the bit d3 low, the clamp voltage is 3v. bit d2 controls the power-down mode. setting bit d2 high will place the HT82V26A into a very low power sleep mode. all register contents are retained while the HT82V26A is in the power-down state. setting bit d1 high will configure the HT82V26A for the digital output (d0~d7) delay 2ns. bit d0 controls the output mode of the HT82V26A. setting bit d0 high will enable a single byte output mode where only 8 msbs of the 16b adc is output. if bit d0 is set low, then the 16b adc output is multiplexed into two bytes.
HT82V26A rev. 1.00 7 august 16, 2005 d8 d7 d6 d5 d4 d3 d2 d1 d0 set to 0 set to 0 set to 1 3 channels cds operation clamp bias power-down output delay 1 byte out (high-byte only) 1=on* 1=cds mode* 1=4v* 1=on 1=on 1=on 0=off 0=sha mode 0=3v 0=off (normal)* 0=off* 0=off* configuration register settings note: * power-on default value mux register the mux register controls the sampling channel order and the 2-channel mode configuration in the HT82V26A. bits d8 should always be set low. bit d7 is used when operating in the 3-channel mode or the 2-channel mode. setting bit d7 high will sequence the mux to sample the red channel first, then the green channel, and then the blue channel. when in the 3-channel mode, the cdsclk2 rising edge always resets the mux to sample the red channel first (see timing diagrams). when bit d7 is set low, the channel order is reversed to blue first, green second, and red third. the cdsclk2 rising edge will always reset the mux to sample the blue channel first. bits d6, d5 and d4 are used when operating in 1 or 2-channel mode. bit d6 is set high to sample the red channel. bit d5 is set high to sample the green channel. bit d4 is set high to sample the blue channel. the mux will remain stationary during 1-channel mode. the two channel mode is selected by setting two of the channel select bits (d4~d6) high. the mux samples the channels in the order selected by bit d7. bits d0~d3 are used for controlling cdsclk1, cdsclk2 and adcclk internal delay. d8 d7 d6 d5 d4 d3 d2 d1 d0 set to 0 mux order channel select enable delay cds1 delay cds2 delay adck delay 1=r-g-b* 0=b-g-r 1=red* 0=off 1=green 0=off* 1=blue 0=off* 0=off 0=2ns* 0=2ns* 0=0ns* 1=on* 1=4ns 1=4ns 1=2ns mux register settings note: * power-on default value pga gain registers there are three pga registers for use in individually programming the gain in the red, green and blue channels. bits d8, d7 and d6 in each register must be set low, and bits d5 through d0 control the gain range in 64 increments. see figure for a graph of the pga gain versus pga register code. the coding for the pga registers is a straight binary, with an all zero words corresponding to the minimum gain setting (1x) and an all one word corresponding to the maximum gain setting (5.85x). the HT82V26A uses one programmable gain amplifier (pga) for each channel. each pga has a gain range from 1x (0db) to 5.85x (15.3db), adjustable in 64 steps. the figure shows the pga gain as a function of the pga register code. although the gain curve is approximately linear in db, the gain in v/v varies in nonlinear proportion with the register code, according to the following the equation: gain= 5.85 1 4.85x( 63 g 63 ) + - where g is the decimal value of the gain register contents, and varies from 0 to 63. - 2 2 2 2 - 1 2 2 - 0 2 2 - % 2 2 - 2 2 2 2 0 1 2 2 0 0 2 2 0 % 2 2 / - 2 2 / 2 2 1 1 0 % / - 1 / % / / 1 0 1 1 - 1 1 " 5 2 3 2 2 2 2 2 2 2 2 2 2 2 2 2 4 " ) 6 ) 2 3 2 2 2 2 2 2 2 2 2 2 2 2 2 4 2 2 7 ! 2 2 # ' ! pga gain transfer function
timing diagrams HT82V26A rev. 1.00 8 august 16, 2005 - 1 . / 0 - 1 + , ( 8 6 9 : 8 % serial write operation timing - 1 . / 0 - 1 + , ( ) 6 9 : 8 % serial read operation timing d8 d7 d6 d5 d4 d3 d2 d1 d0 gain (v/v) gain (db) set to 0 set to 0 set to 0 msb lsb 1.0 1.013 . . . 5.43 5.85 0.0 0.12 . . . 14.7 15.3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 1 0 0 . . . 1 1 0 0 1 1 0 0 1 1 0* 1 0 1 pga gain register settings note: * power-on default value offset registers there are three offset registers for use in individually programming the offset in the red, green, and blue channels. bits d8 through d0 control the offset range from 250mv to 250mv in 512 increments. the coding for the offset registers is sign magnitude, with d8 as the sign bit. the table shows the offset range as a function of the bits d8 through d0. d8 d7 d6 d5 d4 d3 d2 d1 d0 offset (mv) msb lsb 0 0 0 1 1 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 . . . 1 0 0 . . . 1 0 0 1 0 0 1 0 0 1 0 0 1 0* 1 1 0 1 1 0 0.98 . . . 250 0 0.98 . . . 250 note: * power-on default value
HT82V26A rev. 1.00 9 august 16, 2005 2 3 - 4 , , - , ( & 2 . ; 1 8 < = > = 8 < = > = 8 < = > = 8 < = > = 8 < = > = 8 < = > = 8 < = > = - , ( 2 3 - 4 2 3 - 4 2 3 - 4 2 3 4 2 3 4 2 3 4 2 3 4 2 3 4 2 3 4 2 3 4 2 3 4 2 3 4 2 3 4 2 3 4 ! 2 " & 3 ? 2 ? 2 4 @ ! 2 3
4 @ ! 2 3
0 4 @ ! 2 3
/ 4 - - - - , 8 < = 3-channel ccd mode timing (select r-g-b mode) , , - , ( & 2 . ; 1 8 < = > = 8 < = > = 8 < = > = 8 < = > = 8 < = > = 8 < = > = 8 < = > = - , ( 2 3 4 2 3 - 4 2 3 - 4 2 3 - 4 2 3 - 4 2 3 4 ! 2 " & 3 ? 2 4 @ ! 2 3
4 @ ! 2 3
0 4 - : - - , 8 < = 2 3 0 4 2 3 0 4 2 3 4 2 3 4 2 3 4 2 3 4 2 3 4 2 3 4 2 3 4 @ ! 2 3
/ 4 @ ! 2 3
4 : 2-channel ccd mode timing (select g-b mode)
HT82V26A rev. 1.00 10 august 16, 2005 , , - , ( & 2 . ; 1 8 < = > = 8 < = > = 8 < = > = 8 < = > = 8 < = > = 8 < = > = 8 < = > = * , ( ! 2 " & @ ! 3
/ 4 - - , 8 < = @ ! 3 . 4 @ ! 3 4 @ ! 3 4 @ ! 3 / 4 @ ! 3 / 4 @ ! 3 0 4 @ ! 3 0 4 @ ! 3 4 @ ! 3 4 @ ! 3 - 4 @ ! 3 - 4 @ ! 3 4 @ ! 3 4 @ ! 3 4 @ ! 3 4 @ ! 3
4 - - @ ! 3
4 @ ! 3
. 4 @ ! 3
% 4 @ ! 3
4 @ ! 3
1 4 @ ! 3
4 1-channel ccd mode timing 2 3 - 4 , - , ( & 2 . ; 1 8 < = > = 8 < = > = 8 < = > = 8 < = > = 8 < = > = 8 < = > = 8 < = > = - ( 2 3 - 4 2 3 - 4 2 3 - 4 2 3 4 2 3 4 2 3 4 2 3 4 2 3 4 2 3 4 2 3 4 2 3 4 2 3 4 2 3 4 2 3 4 ! 2 " & 3 ? 2 ? 2 4 - - , 8 < = - @ ! 2 3
4 @ ! 2 3
0 4 @ ! 2 3
/ 4 3-channel sha mode timing (select r-g-b mode)
HT82V26A rev. 1.00 11 august 16, 2005 , - , ( & 2 . ; 1 8 < = > = 8 < = > = 8 < = > = 8 < = > = 8 < = > = 8 < = > = 8 < = > = - ( 2 3 4 2 3 - 4 2 3 - 4 2 3 - 4 2 3 - 4 2 3 4 - , 8 < = 2 3 0 4 2 3 0 4 2 3 4 2 3 4 2 3 4 2 3 4 2 3 4 2 3 4 2 3 4 , - : - : - : @ ! 2 3
4 @ ! 2 3
0 4 @ ! 2 3
/ 4 ! 2 " & 3 ? 2 4 @ ! 2 3
4 2-channel sha mode timing (select g-b mode) , - , ( & 2 . ; 1 8 < = > = 8 < = > = 8 < = > = 8 < = > = 8 < = > = 8 < = > = 8 < = > = - * , ( , 8 < = @ ! 3 . 4 @ ! 3 4 @ ! 3 4 @ ! 3 / 4 @ ! 3 / 4 @ ! 3 0 4 @ ! 3 0 4 @ ! 3 4 @ ! 3 4 @ ! 3 - 4 @ ! 3 - 4 @ ! 3 4 @ ! 3 4 @ ! 3 4 @ ! 3 4 @ ! 3
4 - ! 2 " & - - * - @ ! 3
/ 4 @ ! 3
4 @ ! 3
. 4 @ ! 3
% 4 @ ! 3
4 @ ! 3
1 4 @ ! 3
4 1-channel sha mode timing
application circuits the recommended circuit configuration for the 3-channel cds mode operation is shown in the figure below. the rec - ommended input coupling capacitor value is 0.1 f. a single ground plane is recommended for the HT82V26A. a separate power supply may be used for drvdd, the digi - tal driver supply, but this supply pin should still be decoupled to the same ground plane as with the rest of the HT82V26A. the loading of the digital outputs should be minimized, either by using short traces to the digital asic, or by using external digital buffers. to minimize the effect of digital transients during major output code transitions, the falling edge of the cdsclk2 should occur in coincidence with or before the rising edge of adcclk. all 0.1 f decoupling ca - pacitors should be located as close as possible to the HT82V26A pins. when operating in a single channel mode, the unused analog inputs should be grounded. note: for the 3-channel sha mode, all of the above considerations also apply for this configuration, except that the analog input signals are directly connected to the HT82V26A without the use of coupling capacitors. the off - set pin should be grounded if the inputs to the HT82V26A are to be referenced to ground, or a dc offset volt - age should be applied to the offset pin in the case where a coarse offset needs to be removed from the inputs. the analog input signals must already be dc-biased between 0v and 2v, if offset is connected to ground. HT82V26A rev. 1.00 12 august 16, 2005 - % - . - - / - 0 - - - - - 1 % . / - 0 / . % 1 - 0 ) ) ) " ( * * + ) " ) " * + * ) ) ( , + , , - , ( ) ) . 2 3 4 / 0 - 1 2 3 4 1 * 1 * 1 * 1 * 1 * 1 * 1 * 1 * 1 * ) / ) 6 ) 5 2 " & 1 * / ) ! # a " & " & ! " & 1 * 1 * 2 " & ! 2 " & - % - . - - / - 0 - - - - - 1 % . / - 0 / . % 1 - 0 ) ) ) " ( * * + ) " ) " * + * ) ) ( , + , , - , ( ) ) . 2 3 4 / 0 - 1 2 3 4 1 * 1 * 1 * 1 * 1 * 1 * 1 * ) / ) 6 ) 5 2 " & / ) ! # a " & " & ! " & 2 " & ! 2 " & 2 7 !
package information 28-pin ssop (209mil) outline dimensions symbol dimensions in mil min. nom. max. a 291 323 b 196 220 c9 15 c 396 407 d65 73 e 25.59 f4 10 g26 34 h4 8 0 8 HT82V26A rev. 1.00 13 august 16, 2005 - % / 0 * b 8
28-pin sop (300mil) outline dimensions symbol dimensions in mil min. nom. max. a 394 419 b 290 300 c14 20 c 697 713 d92 104 e 50 f4 g32 38 h4 12 0 10 HT82V26A rev. 1.00 14 august 16, 2005 - % / 0 * b 8
product tape and reel specifications reel dimensions sop 28w (300mil) symbol description dimensions in mm a reel outer diameter 330 1.0 b reel inner diameter 62 1.5 c spindle hole diameter 13.0+0.5 0.2 d key slit width 2.0 0.5 t1 space between flange 24.8+0.3 0.2 t2 reel thickness 30.2 0.2 HT82V26A rev. 1.00 15 august 16, 2005 + + -
carrier tape dimensions sop 28w (300mil) symbol description dimensions in mm w carrier tape width 24.0 0.3 p cavity pitch 12.0 0.1 e perforation position 1.75 0.1 f cavity to perforation (width direction) 11.5 0.1 d perforation diameter 1.5+0.1 d1 cavity hole diameter 1.5+0.25 p0 perforation pitch 4.0 0.1 p1 cavity to perforation (length direction) 2.0 0.1 a0 cavity length 10.85 0.1 b0 cavity width 18.34 0.1 k0 cavity depth 2.97 0.1 t carrier tape thickness 0.35 0.01 c cover tape width 21.3 HT82V26A rev. 1.00 16 august 16, 2005 9 1 * , 1 1 1
HT82V26A rev. 1.00 17 august 16, 2005 copyright
2005 by holtek semiconductor inc. the information appearing in this data sheet is believed to be accurate at the time of publication. however, holtek as - sumes no responsibility arising from the use of the specifications described. the applications mentioned herein are used solely for the purpose of illustration and holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. holtek s products are not authorized for use as critical components in life support devices or systems. holtek reserves the right to alter its products without prior notification. for the most up-to-date information, please visit our web site at http://www.holtek.com.tw. holtek semiconductor inc. (headquarters) no.3, creation rd. ii, science park, hsinchu, taiwan tel: 886-3-563-1999 fax: 886-3-563-1189 http://www.holtek.com.tw holtek semiconductor inc. (taipei sales office) 4f-2, no. 3-2, yuanqu st., nankang software park, taipei 115, taiwan tel: 886-2-2655-7070 fax: 886-2-2655-7373 fax: 886-2-2655-7383 (international sales hotline) holtek semiconductor inc. (shanghai sales office) 7th floor, building 2, no.889, yi shan rd., shanghai, china 200233 tel: 021-6485-5560 fax: 021-6485-0313 http://www.holtek.com.cn holtek semiconductor inc. (shenzhen sales office) 5/f, unit a, productivity building, cross of science m 3rd road and gaoxin m 2nd road, science park, nanshan district, shenzhen, china 518057 tel: 0755-8616-9908, 8616-9308 fax: 0755-8616-9533 holtek semiconductor inc. (beijing sales office) suite 1721, jinyu tower, a129 west xuan wu men street, xicheng district, beijing, china 100031 tel: 010-6641-0030, 6641-7751, 6641-7752 fax: 010-6641-0125 holtek semiconductor inc. (chengdu sales office) 709, building 3, champagne plaza, no.97 dongda street, chengdu, sichuan, china 610016 tel: 028-6653-6590 fax: 028-6653-6591 holmate semiconductor, inc. (north america sales office) 46729 fremont blvd., fremont, ca 94538 tel: 510-252-9880 fax: 510-252-9885 http://www.holmate.com

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